Supercomputing with commodity CPUs: Are mobile SoCs ready for HPC?
… Tree code for N-body problem HYDRO … Villavieja, N. Puzovic, and A. Ramirez. The low
power architecture approach towards exascale computing. …
power architecture approach towards exascale computing. …
Tibidabo: Making the case for an ARM-based HPC system
… n c p c is the number of cores per chip. P o v e r represents the total Tibidabo cluster power
… in the Tibidabo cluster ( n t c = 192 ). We explore the total number of cores per chip ( n c p c ) …
… in the Tibidabo cluster ( n t c = 192 ). We explore the total number of cores per chip ( n c p c ) …
The low-power architecture approach towards exascale computing
Energy efficiency is a first-order concern when deploying any computer system. From battery-operated
mobile devices, to data centers and supercomputers, energy consumption limits …
mobile devices, to data centers and supercomputers, energy consumption limits …
Energy efficiency vs. performance of the numerical solution of PDEs: An application study on a low-power ARM-based cluster
… -called ‘mesh chunk’ of angular size 90 × 90 centred on the North pole and we implement
an earthquake source near the North pole. The model of the structure of the Earth is the elastic …
an earthquake source near the North pole. The model of the structure of the Earth is the elastic …
The evolution of gene-specific transcriptional noise is driven by selection at the pathway level
… F* with the ratio of Ka/Ks, as measured by sequence comparison between mouse genes and
their human orthologs, after discarding genes with evidence for positive selection (n = 5). In …
their human orthologs, after discarding genes with evidence for positive selection (n = 5). In …
[HTML][HTML] Inference of recombination maps from a single pair of genomes and its application to ancient samples
… HMM is an HMM with n = t × k hidden states (Fig 1). The transition matrix of the Markov-modulated
process, Q iSMC , has dimension n × n and is obtained from Q ρ and Q SMC : (3) …
process, Q iSMC , has dimension n × n and is obtained from Q ρ and Q SMC : (3) …
Experiences with mobile processors for energy efficient HPC
The performance of High Performance Computing (HPC) systems is already limited by their
power consumption. The majority of top HPC systems today are built from commodity server …
power consumption. The majority of top HPC systems today are built from commodity server …
Dta-c: A decoupled multi-threaded architecture for cmp systems
One way to exploit Thread Level Parallelism (TLP) is to use architectures that implement
novel multithreaded execution models, like Scheduled Data- Flow (SDF). This latter model …
novel multithreaded execution models, like Scheduled Data- Flow (SDF). This latter model …
Data placement in HPC architectures with heterogeneous off-chip memory
M Pavlovic, N Puzovic… - 2013 IEEE 31st …, 2013 - ieeexplore.ieee.org
The performance of HPC applications is often bounded by the underlying memory system's
performance. The trend of increasing the number of cores on a chip imposes even higher …
performance. The trend of increasing the number of cores on a chip imposes even higher …
Implementing fine/medium grained tlp support in a many-core architecture
… Inputs are two n by n matrices. ─ Zoom is a image processing kernel for zooming. It is
parallelized by sending different parts of the picture to different processors. Input is an n by n …
parallelized by sending different parts of the picture to different processors. Input is an n by n …